Thank you, Monica, and thanks, everyone, for joining us on the call today. We are pleased to report fourth quarter results with revenue of $14.8 million and non-GAAP EPS of $0.11 per diluted share with revenue towards the high end of our guidance range and EPS in line with our expectations. Our performance this quarter was driven by strength in data center, energy management and industrial automation applications. Growth in data center was driven by our ongoing work with IBM on the FCM4 module as well as its recently introduced FCM5 and the redundant array of independent disks or RAID reference design at the top 5 hyperscale operators. Within Energy Management and Industrial Automation, we saw demand return to normal levels after a period of inventory consumption that dampened demand in the prior year. With respect to below-the-line items, we recognized $2 million in other income in the fourth quarter and $10.5 million to date from the $14.6 million contract we have with a DoD contractor to develop a sustainment plan for our MRAM manufacturing facilities to provide continuous onshore MRAM capabilities to their aerospace and defense customers. We expect this business to progress on schedule with estimated completion in the first half of 2027. On the product side, we had a total of 238 design wins in 2025, up from 178 in the prior year. Our pipeline of new design wins for our MRAM products speaks to the continuing technical innovation from the Everspin team introducing new products to meet customer demand. These design wins support new customers and existing customers with new programs in industrial automation, casino gaming, energy management and military and aerospace applications. Turning to some of our product development efforts. We continue to expand our xSPI STT-MRAM portfolio in response to demand from our customers. We are pleased to announce that during the fourth quarter, we ramped our PERSYST 64-megabit xSPI STT-MRAM high reliability product to full production and saw strong demand driven by new customer interest and design wins, specifically in the low earth orbital or LEO satellite market. These devices are AEC-Q100 Grade 1 qualified and ideally suited for use in harsh conditions such as 125C Celsius operating temperature with a minimum 10 years of data retention. These capabilities are demanded by our customers to secure critical data in a variety of systems from aerospace and defense to industrial applications, including automotive. We are taking orders to support high-volume production from our customers and began shipping in the current quarter. In addition, we are in the process of qualifying higher density, high reliability parts of 128-megabit and 256-megabit that will be available in high volume in the second half of this year. We are on track to tape out a monolithic 256-megabit xSPI STT-MRAM device on a 16-nanometer FinFET node at TSMC in the second half of this year. This part will be our first product in the UNISYST family, unifying code storage and data memory in a high-density, nonvolatile architecture for edge AI, industrial and mission-critical designs. It is designed to deliver high bandwidth read and write speeds in a nonvolatile memory device, enabling fast boot, rapid updates and predictable performance without the trade-offs of traditional flash-based designs. By combining high-speed access with persistent storage, this family of parts will support software design systems that require frequent reconfiguration while maintaining data integrity across power cycles. As part of our efforts to build on to our partner network, we recently qualified our PERSYST 64-megabit xSPI STT-MRAM for Microchip's PIC64-HPSC series of 64-bit microprocessors or MPUs and are supporting the ecosystem for components being qualified by Microchip. This ecosystem includes several industry partners that jointly offer solutions tailored for the harsh environmental conditions in space. The high-density, high reliability xSPI STT-MRAM parts I discussed earlier would be an ideal solution for this application. MRAM is achieving significant success as a leading embedded nonvolatile memory in IoT, automotive and AI edge devices, yet the densities and performance options of embedded MRAM macros have been limited. At the same time, the semiconductor industry is moving towards chiplets to overcome rising costs, manufacturing complexity and yield limitations of traditional large monolithic chips, especially when combining leading-edge logic with volatile or nonvolatile memory. Chiplets enable mix and match process nodes, greater customization and reuse of building blocks, providing new freedom of degrees in the form of heterogeneous packaging solutions. With organizations such as the Open Compute project, embracing chiplets from the hyperscale data center to the edge, it is foreseeable that chiplets will be ubiquitous. This trend increasingly favors Everspin given our focus on marketing chip solutions, including chiplets and licensing our technology to embedded MRAM partners. In 2025, we further advanced our efforts in this area through several initiatives. We engaged with the Fraunhofer Chiplet Center of Excellence to analyze next-generation automotive compute platforms and corresponding MRAM use cases. We subsequently progressed to engage on system-level simulations into which we plan to provide MRAM simulation models to allow an assessment as well as quantification of the benefits that MRAM can provide in various use cases. Everspin is also participating in an effort to bring MRAM chiplets to the IMEC ecosystem that is aligned with the framework of the Open Compute Project chiplet work streams. IMEC launched the Automotive Chiplet Forum in 2024 to bring together members from the automotive industry to enable an open chiplet ecosystem essential for accelerating innovation, reducing costs and reinforcing the supply chain. More recently, we joined the newly formed Physical AI Chiplet Ecosystem or PACE, to help enable MRAM-based solutions for physical AI. As part of this effort to co-develop interoperable and reusable chiplets to reduce development costs and speed time to market for system and ASIC companies, Everspin will provide a robust, high-performance, nonvolatile memory to assist securing pace chiplets for boot, weight and code storage as well as life cycle management solutions. We expect to see chiplets addressing various applications over the next few years. As a reminder, the chiplet is part of our UNISYST unified code and data memory solutions, which are currently in the design phase. To further enhance our position in the auto industry, we are working with Quintauris, a joint venture of leading semiconductor companies on a next-generation RISC-V-based automotive reference design platform. RISC-V is an open standard instruction set architecture or ISA based on reduced instruction set computer or RISC principles, allowing anyone to design, manufacture and sell chips without paying a license fee for the ISA. Its modular architecture allows designers to create purpose-built accelerators using RISC-V core technology as well as extensions. This also includes new instructions that uniquely integrate and leverage MRAM as a persistent working memory. Given its rapid adoption, it offers a greenfield opportunity to create new MRAM-based architectures that fully utilize all the features and benefits that MRAM has to offer. Before I close, I would like to discuss our long-term strategy, which entails reaching $100 million in annual revenue over the next 3 to 5 years. We believe this growth will be driven by the ramp of new products, most notably our new XY parts in our PERSYST product portfolio, such as the 64-megabit part I described earlier and continued solid growth in our Toggle MRAM and licensing business. Our new PERSYST X5 parts are getting solid traction. They are offered in densities from 4 megabit to 256-megabit and include the power-optimized SC families and the high reliability or HR families with quad and optical SPI interfaces. For example, in industrial automation, energy management, electric vehicle and casino gaming markets, reliable high-density memory is required for next-generation systems. In aerospace and defense markets, such as LEO satellites, flight control systems require reliable, fast read and write speeds and fast boot for configuration. And in the FPGA and the MPU markets for Edge AI, low standby power, instant on and high-density memory is needed for larger bitstreams. We expect our first enhanced Serial NOR like UNISYST product family to be in production in 2027 and anticipate these products to contribute to our $100 million revenue target. Before I turn the call over to Bill to walk through our financials and guidance, I would like to briefly touch on the industry environment. As has been widely publicized, the industry is expecting -- experiencing memory shortages. Memory suppliers who have for decades been pushed into commoditization have been -- have seen a shift based on unprecedented memory shortages driven by the demands of AI. As a result, they have gone into allocation mode and are moving their capacity up the food chain. Companies that can make NOR flash, NAND and DRAM are shifting those capacities to where they can get more margin out of their fixed capacity. NOR suppliers, for example, are converting their lines to support DRAM to maximize their margins and generate more revenue. This has created a gap in the supply for NOR flash and driving customers to look for alternatives. We are in conversations with customers to evaluate our xSPI STT-MRAM to replace NOR flash. We have the capacity to support such demand and our parts are compatible with NOR flash. While these market dynamics are speeding up such conversations, revenue is contingent upon the qualification cycles of our potential customers. I will now turn it over to our CFO, Bill Cooper, who will walk you through our fourth quarter financials and first quarter 2026 guidance. Bill?