Good afternoon. In Q1, we continued our strong momentum with revenue in the upper end of our guidance range and non-GAAP EPS surpassing the upper end of our guidance range. Revenue was $1.65 billion, up 21% year-over-year. Non-GAAP operating margin was 38.7% up approximately 3.5 points year-over-year. Non-GAAP EPS was $3.56, up 36% year-over-year. While maintaining our laser focus on meeting our quarterly financial commitments, we strategically drive the business for long-term financial success. Over the last three years, we have delivered a 17% of revenue CAGR, non-GAAP operating margin improvement of 7 points and non-GAAP EPS growth at a 26% CAGR. Shelagh will discuss our financials and guidance in more detail. Let's turn to market trends. We've entered an era of pervasive intelligence, driven by the rise of artificial intelligence, silicon proliferation and software-defined systems. These trends demand more compute, new architectures and new design methodologies who are requiring us to address the significant challenges of complexity, cost, energy consumption and security. Despite the mounting challenges, design starts continue to rise as the semiconductor industry scales to $1 trillion in revenue or more by the end of the decade. As the leading silicon to system design solution company with best-in-class EDA tools and the broadest portfolio of semiconductor IP, Synopsys growth opportunity is truly incredible and already underway. Across industries, a paradigm shift is underway as companies race to deliver on this era of pervasive intelligence where AI and smart technologies are omnipresent and interconnected. To capitalize on this shift, the technology is overcoming is converging on a silicon to systems approach to innovation. As the company at the heart of silicon and systems, Synopsys was made for this moment. There is no one more capable of helping companies innovate for this era of pervasive intelligence. Semiconductor companies are now designing with a system approach in mind, while system companies are unlocking additional value through purpose-built chips and software-defined systems. At the same time, customers see the fusion of electronics design and physics simulation as critical to delivering high-performing and high-yielding solutions for their business. Building on our seven-year partnership with Ansys, the industry leader in simulation and a bit multiyear strategy to reshape our business to support system-level design. Last month, we announced our intent to acquire Ansys. This transaction will grow our TAM by 1.5 times to $28 billion and further enhance our silicon to system strategy. Both across our core EDA segment and a highly attractive adjacent growth areas where Ansys has an established presence and successful go-to-market expertise. Customer feedback on the proposed transaction has been incredibly supportive, and we look forward to closing this transaction in the first half of 2024. Now I'll share some segment highlights starting with Design Automation, where we saw strong design win activity across the business. We continue to enhance our leadership in digital EDA as our capabilities become increasingly critical for the leading chips at advanced nodes. We are proud to have partnered with our customers to achieve a number of industry firsts in Q1. The world's first GAA-based next generation arm, Cortex-X mobile core tape-out at a leading Asian mobile SoC provider. The first completed tape-out for a server SoC on 18A. And Asia's first N5 arm flagship automotive core tape-out for a leading EV OEM. In addition, we had multiple competitive wins anchored by 2-nanometer and 3-nanometer projects at a leading Asian mobile semiconductor company. We are also gaining momentum with analog mixed-signal customers. We won several competitive full flow displacements at analog mixed signal companies including networking OEMs in Europe and Japan. A key differentiator in these competitive wins was the breadth and leadership of our EDA platform, from digital to analog and from architecture to sign off. All turbo charged with the industry's leading full-flow AI platform, synopsys.ai. Synopsys.ai focuses on three distinct pillars of value for our customers, optimization, XSO.ai beat analytics, and generative AI, including our copilot. Starting with our XSO.ai family, which includes design, verification, test and analog space optimization. We continue to expand our footprint and drive set in our core EDA tools. DSO.ai was key in several major wins and continues to drive a 20% plus uplift to Fusion Compiler revenue at multiple accounts. Increasing share of usage of DSO.ai were competition was driven by superior PPA results on our platform versus alternatives. We saw a very strong pull for VSO.ai with multiple production deployments that are seeing excellent improvements in test coverage and turnaround time. A large North American HPC semiconductor company made a significant investment in VSO.ai technology with plans to immediately deploy on four projects and eventually deploy corporate-wide. Another large North American GPU company saw 2 times faster turnaround time and a 20% improvement in coverage and is planning a large-scale deployment of the technology. Our analog tool, ASO.ai now has multiple deployments moving to production with reference flows at TSMC, Samsung and Intel for analog migration. We also brought in the capability of TSO.ai, adding a design for test feature to the proven ability for advanced pattern generation. At the International Test Conference this quarter, we demonstrated a 20% reduction in total pattern count using TSO.ai. Our data analytics AI products also saw significant logo engagement growth. A great example is Silicon.da production analytics, which is part of the silicon lifecycle management family and spans design through product manufacturing phases. Silicon.da automatically highlights silicon data outliers, enabling engineering teams to quickly identify and correct underlying issues in design and manufacturing and boost productivity. Last quarter, we had a groundbreaking generative AI announcement with Microsoft for accelerating chip design, Synopsys.ai copilot. The integration of Gen AI across Synopsys.ai provides chip designers with collaborative capabilities that offer expert tool guidance, generative capabilities to enable RTL and collateral creation from natural language. Following positive feedback from initial pilot participants, AMD, Intel and Microsoft will be adding a number of other companies with our beta rollout. In Q1, we also won significant multi-die package designs. Our 3DIC Compiler platform gained substantial momentum in multi-die packaging. Multi-die implementations continue to increase in the HPC market with an expectation that by 2028, 40% of HPC designs will be multi-die architectures. Like the transition to AI this new design paradigm will create significant opportunity for both our EDA and IP businesses. Moving to our systems business. Hardware-assisted verification had a strong quarter with excellent booking on