Good afternoon. We delivered excellent results in the second quarter exceeding all our guidance targets while reaching another quarterly revenue record. Revenue of $1.395 billion was above the high end of our guidance range, with non-GAAP operating margin at 33.3%. GAAP earnings per share was $1.76, while non-GAAP earnings per share was above the high end of our target range at $2.54. We generated 703 million of operating cash flow and increased our backlog to 7.3 billion. The market is playing out much as we expected when we planned the year. Demand is weaker for semiconductors overall with consumer markets most impacted. Despite choppy macroeconomic conditions, customers continue to prioritize R&D for new chip designs so that they emerge stronger when demand accelerates. The transition to Smart Everything is well underway and will drive significant long-term growth for semiconductors and outsized contribution for us. Against this backdrop, we planned and are executing accordingly. Based on continued strong design activity and high confidence in our business, we are raising our full year revenue guidance range to between $5.79 billion and $5.83 billion. We're increasing our year-over-year non-GAAP ops margin improvement expectation to 150 basis points, up approximately 0.5 versus prior guidance. We are raising our full year non-GAAP EPS range to between $10.77 and $10.84. Shelagh will discuss the financials in more detail. Let me give some color for the quarter. In March, we held SNUG our yearly Synopsys Users Group Conference in Silicon Valley, including its follow on road shows we bring together over 12,000 passionate design engineers around our common focus of driving innovation in chip and system design. Life after three years of COVID, the conference was fantastically engaging. Our audience fully recognized how design parameters and product requirements have become exponentially more complex and interwoven, accelerated by the breakthroughs of multi-die designs. Simultaneously, the end market hunger for Smart Everything puts huge pressure on increasing performance-per-watt to the limit. And on top of that, security and safety are now becoming mandatory everywhere. Synopsys' vision and mission of smart, secure and safe thus sets both a high bar and foreshadows great opportunities for our customers and our company. Users told me, though, that while system complexities are growing exponentially, design resources are not. Design productivity thus requires a catalytic step function change in our approach. To us, this inflection comes from AI. We are embedding AI in everything we do. We have made world class advances in design flow automation and our customers are now adopting synopsis AI on production designs at a remarkable rate. This is not by accident. 12 years ago, we called out a vision of Smart Everything unleashed by the intersection of big data and machine learning. Since then, we applied ML everywhere on our product offering. In 2017, we decided to harness AI for entire design subflows and began investing in DSO.ai where DSO stands for Design Space Optimization. We rapidly progressed from prototype to customer validation of AI driven results in 2019, recognized by the ASPENCORE IEEE World Electronics Achievement Award for Innovative Product of the Year in 2020. The following year, at the 2021 HOT CHIPS Conference, we unveiled our pioneering AI journey and roadmap showcased by a slew of remarkable results. DSO.ai delivered not only better speed and power on large and complex design blocks, but it did so in a fraction of the time meaning month down to weeks, while requiring fewer, less specialized designers. This did not go unnoticed as it had been validated weeks earlier by Samsung, an early partner announcing the world's first AI driven commercial tapeout with DSO.ai. By the end of 2022, adoption, including nine of the top ten semiconductor vendors, had moved forward at great speed with 100 AI driven commercial tapeouts. Today, the tally is well over 200 and continues to increase at a very fast clip as the industry broadly adopts AI for design from Synopsys. But we have not sat still. At SNUG, we unveiled the industry's first full stack AI driven EDA suite Synopsys.ai Specifically in parallel to second generation advances in DSO.ai, we announced VSO.ai which stands for Verification Space Optimization and TSO.ai, Test Space Optimization. In addition, we are extending AI across the design stack to include analog design and manufacturing. Partners in the announcement included Nvidia, TSMC, MediaTek, Renesas and IBM Research, all providing stunning use cases of the rapid progress and criticality of Synopsys.ai to deliver their breakthrough results. As an example, Renesas achieved up to 10X improvement in reducing functional coverage holes and up to 30% increase in verification productivity. This is substantial progress. Yet it's still only the beginning of our AI journey. The roadmap of optimizing, automating and generative AI use cases is wide open to deliver productivity breakthroughs for years to come. Turning now to our segment results, let me start with design automation, which accounts for roughly 65% of Synopsys revenue. Design automation had a very strong quarter with robust order and revenue growth. Let me lead off by recognizing the one year anniversary of Synopsys Cloud, the industry's first and only SaaS solution that provides customers with a completely browser-based experience, optimized compute and preconfigured EDA flows. We're seeing excellent momentum as customers gain significant time to market advantages with the industry's only cloud optimized pay-per-use business model providing on demand tool access with cloud scale elasticity. In the past year, we have doubled our customer base every quarter this year with the SaaS model accounting for 70% of users. Market adoption of our fusion compiler continues to grow across vertical segments and manufacturing nodes. This quarter we won many major designs, including wins at two top Asian semiconductor companies and a leading high performance computing company. Fusion compiler is a leading advanced three nanometer node tapeout with roughly two-thirds of designs exclusively using Synopsys flows. We continue to drive our design automation leadership. In Q2, we announced a collaboration with TSMC to deliver digital and custom design EDA flows on their most advanced two nanometer process node. Our full EDA stack complemented with the timeless timeliness of IP offering, allows designers to jumpstart their two nanometer designs, differentiate their SOCs and accelerate their time to market. Expanding from digital, we continue to grow and displace competition in the custom design market. We earned eight new design wins in Q2, giving us 23 wins year-to-date. We also benefit from a growing pipeline of top customers using Synopsys for advanced node retargeting. Transitioning to multi-die chip design we're leading the industry's transformation from monolithic SoCs to multi-die systems with a comprehensive and scalable solution for fast, heterogeneous integration. In Q2, we deployed our multi-die VCS functional verification at a leading US high performance computing customer, delivering more than 2X faster turnaround time. We also announced our collaboration with TSMC and Ansys for multi-die system design and manufacturing, providing the industry's most comprehensive EDA and IP solutions on TSMC's advanced process technologies. We've often talked about the unbounded demands for verification. The need for verification acceleration is unrelenting. Our customers want more, more throughput, more capacity and more energy efficiency, all with lower total cost of ownership. This quarter we announced