Thank you, Erica, and thanks to everyone for joining us on our call today. In the second quarter of 2025, we achieved record annual contract value plus royalties of $69.1 million. We exited the quarter with $99.3 million in remaining performance obligations or RPO, highlighting the growing demand for our system IP technology. During the second quarter, we saw increased adoption, particularly in enterprise computing and automotive applications, driven largely by proliferation of AI computing, where the speed and reliability of data movement enabled by Arteris is paramount. One of these strategic wins was AMD, a global leader in high-performance and adaptive computing and a top 10 semiconductor company by revenue, which signed an agreement to utilize Arteris FlexGen, smart network-on-chip IP, the technology we announced earlier this year. FlexGen will aim to provide high-performance data transport in AMD chiplets, powering AI across AMD's broad portfolio, which spans from data centers to edge and end devices. It will also be used in combination with AMD Infinity Fabric interconnect, underscoring the increasing complexity of modern SoCs and chiplet-based architectures, which now require multiple highly specialized interconnects or NoCs. In addition to the AMD relationship, we now have over 2 dozen FlexGen installations at multiple customers and anticipate that this product will contribute to our revenue over time. We believe FlexGen is a breakthrough technology in terms of productivity and optimization of SoC data movement. I'm proud that Arteris was recently recognized in the 8th Annual AI Breakthrough Awards, with FlexGen winning the AI Engineering Innovation Award from among the over 5,000 global nominations. FlexGen was recognized for its ability to successfully automate critical aspects of NoC IP creation, ensuring rapid, correct-by-design interconnect fabrics that optimize performance and efficiency of AI-driven SoCs. Another recent AI-related customer win was Whalechip, a fabless semiconductor provider that specializes in developing data center ASICs and processors for high-bandwidth applications, including cloud servers, interconnect computing and blockchain computing, among others. As the semiconductor industry accelerates efforts to increase performance and efficiency, especially driven by AI workloads, we are seeing a growing shift from traditional monolithic chips toward multi-die or chiplet architectures in the AI era. Consequently, during the second quarter, we announced an expansion of our multi-die solution, which we believe delivers further foundational technology for rapid chiplet-based innovation. This includes broader standard support for the Universal Chiplet Interconnect Express, or UCIe, collaboration and extended support for Arm AMBA protocols, chiplet interface collaborations with Synopsys and Cadence, and RISC-V ecosystem support with partners such as Andes, SiFive and Tenstorrent. Moreover, the Arteris expanded multi-die solution has been developed in close partnership with key customers who are increasingly designing chiplets such as Renesas. For example, Arteris technologies is used to provide underlying data transport and connectivity in the fifth generation of the R-Car automotive silicon developed by the high-performance computing SoC business unit. Arteris multi- die solutions help Renesas deliver on the integration and scalability offered by multi-die SoCs as AI applications push the limit of performance and power efficiency. Lastly, as the number of chiplets in multi-die SoCs increases, so does the underlying number of individual IP blocks. As such, it becomes increasingly important to properly and reliably package and prepare hundreds or even thousands of these IP components for effective integration and reuse across SoCs, chiplets and complex IP subsystems. To capitalize on this trend in the second quarter, we announced Magillem Packaging, a new software product designed to automate IP packaging to simplify and speed up the process of assembling silicon chiplets and chips. Utilizing the latest version of the IEEE 1685 IP-XACT standard, Magillem Packaging is designed to work seamlessly with industry tools and silicon IP with the goal of helping companies meet increasing design demands, while reducing costly errors and delays associated with integrating an ever-growing number of IP blocks, and the associated rising system complexity. We believe the scale and scope of our opportunity remain robust, supported by our current products and strong product pipeline of new silicon system IP technologies, as well as growing relationships with the largest and most advanced electronics companies in the world. Our customers continue to innovate in exciting high-growth areas, including across multiple applications of AI from data centers to the edge, autonomous driving, advanced communications, consumer and industrial use cases. While we continue to diligently monitor the current global economic uncertainty, this did not lead to any deal cancellations or delays in the second quarter. In addition, we are seeing opportunities for customers to accelerate outsourcing of their system IP needs to Arteris, in order to accelerate their products time-to-market, reduce their own costs and increase their operating efficiencies. Nick will cover these impacts more when he discusses our guidance. With that, I'd like to turn it over to Nick to discuss our financial results in more detail.